W83697HF/F
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID)
Power on default <7:0> = 0001,0000 binary
Bit
Name
Read/Write
Description
7-0
VID
Read Only
Version ID, default is set to 0x10.
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)
This register is defined same as in Bank0.Reg3.
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)
Power on default <7:0> = 0000,0000 binary
Bit
Name
Read/Write
Description
7-0
TMRL
Read/Write Timer Low Byte Register. This is a 12-bit timer (another 4-
bit is defined in Bank1.Reg5) which resolution is 1 ms, that
12
is, the programmed maximum time is 2 -1 ms. The timer
is a down-counter. The timer start down count when the bit
EN_TMR (Enable Timer) of Bank0.Reg2. is set to 1. When
the timer down count to zero and EN_TMR=1, the TMR_I is
set to 1. When the counter down count to zero, a new
initial value will be re-loaded into timer counter.
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH)
Power on default <7: 0> = 0000,0000 binary
Bit
7-4
3-0
Name
Reserved
TMRH
Read/Write
Description
Reserved.
Read/Write Timer High Byte Register. See Bank1.Reg4.
Publication Release Date: Feb. 2002
Revision 0.70
- 62 -
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