W83697HF/F
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode.
Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, will
go to legacy UART mode and clear some register values shown table as follows.
TABLE :BAUD RATE TABLE
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Desired Baud Rate
Decimal divisor used to
generate 16X clock
Percent error difference between
desired and actual
50
75
2304
1536
1047
857
768
384
192
96
**
**
110
0.18%
134.5
150
0.099%
**
**
300
600
**
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
1.5M
**
64
**
58
0.53%
**
48
32
**
24
**
16
**
12
**
6
**
3
**
2
**
1
**
Note 1
0%
1
Note 1: Only use in high speed mode, when Bank0.Reg6.Bit7 is set.
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
Publication Release Date: Feb. 2002
Revision 0.70
- 61 -
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