W83697HF/F
5. CIR RECEIVER PORT
5.1 CIR Registers
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)
Receiver Buffer Register is read only. When the CIR pulse train has been detected and passed by the
internal signal filter, the data samped and shifted into shifter register will write into Receiver Buffer
Register. In the CIR, this port is only supports PIO mode and the address port is defined in the PnP.
5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR)
Power on default <7:0> = 00000000 binary
Bit
Name
EN_GLBI
Read/Write
Description
7
Read/Write Enable Global Interrupt. Write 1, enable interrupt. Write 0,
disable global interrupt.
6-3
2
Reserved
EN_TMR_I
En_LSR_I
EN_RX_I
-
Reserved
Read/Write Enable Timer Interrupt.
1
Read/Write Enable Line-Status-Register interrupt.
Read/Write Receiver Thershold-Level Interrupt Enable.
0
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR)
Power on default <7:0> = 00000000 binary
Bit
7-3
2
Name
Reserved
Read/Write
Description
Reserved
TMR_I
Read Only
Timer Interrupt. Set to 1 when timer count to 0. This bit will
be affected by (1) the timer registers are defined in
Bank4.Reg0 and Bank1.Reg0~1, (2) EN_TMR(Enable
Timer, in Bank0.Reg3.Bit2) should be set to 1, (3)
ENTMR_I (Enable Timer Interrupt, in Bank0.Reg1.Bit2)
should be set to 1.
1
0
LSR_I
Read Only
Read Only
Line-Status-Register interrupt. Set to 1 when overrun, or
parity bit, or stop bit, or silent byte detected error in the
Line Status Register (LSR) sets to 1. Clear to 0 when LSR
is read.
RXTH_I
Receiver Thershold-Level Interrupt. Set to 1 when (1) the
Receiver Buffer Register (RBR) is equal or larger than the
threshold level, (2) RBR occurs time-out if the receiver
buffer register has valid data and below the threshold level.
Clear to 0 when RBR is less than threshold level from
reading RBR.
Publication Release Date: Feb. 2002
- 56 -
Revision 0.70
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