W83697HF/F
4.2.6
Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
7
6
5
0
4
0
3
2
1
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-out
interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to a logical 0.
TABLE 4-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit 3 Bit 2 Bit 1 Bit 0 Interrupt
priority
Interrupt Type
-
Interrupt Source
Clear Interrupt
0
0
0
1
0
1
1
0
-
No Interrupt pending
-
First
UART Receive
Status
1. OER = 1
2. PBER =1
Read USR
3. NSER = 1 4. SBD = 1
1. RBR data ready
0
1
0
0
Second
RBR Data Ready
1. Read RBR
2. FIFO interrupt active level
reached
2. Read RBR until FIFO
data under active level
1
0
1
0
0
1
0
0
Second
Third
FIFO Data Timeout
TBR Empty
Data present in RX FIFO for 4
characters period of time since
last access of RX FIFO.
Read RBR
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
0
0
0
0
Fourth
Handshake status
1. TCTS = 1 2. TDSR = 1
Read HSR
3. FERI = 1
4. TDCD = 1
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
Publication Release Date: Feb. 2002
Revision 0.70
- 53 -
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