W83697HF/F
4.2.9
User-defined Register (UDR) (Read/Write)
This is a temporary register that can be accessed and defined by the user.
TABLE 4-5 BAUD RATE TABLE
BAUD RATE FROM DIFFERENT PRE-DIVIDER
Pre-Div: 13
1.8461M Hz
50
Pre-Div:1.625
14.769M Hz
400
Pre-Div: 1.0
24M Hz
650
Decimal divisor used
to generate 16X clock
Error Percentage between
desired and actual
2304
1536
1047
857
768
384
192
96
**
75
110
600
880
975
1430
**
0.18%
134.5
150
1076
1478.5
1950
0.099%
1200
**
**
300
2400
3900
600
4800
7800
**
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
9600
15600
23400
26000
31200
46800
62400
93600
124800
249600
499200
748800
1497600
**
14400
16000
19200
28800
38400
57600
76800
153600
307200
460800
921600
64
**
58
0.53%
**
48
32
**
24
**
16
**
12
**
6
**
3
**
2
**
1
**
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.
Note. Pre-Divisor is determined by CRF0 of UART A and B.
Publication Release Date: Feb. 2002
Revision 0.70
- 55 -
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