W83697HF/F
4.2.4
Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem
and records changes on these pins.
7
6
5
4
3
2
1
0
toggling (TCTS)
toggling (TDSR)
CTS
DSR
RI falling edge (FERI)
toggling (TDCD)
DCD
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loopback
mode.
Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loopback mode.
Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback
mode.
Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback
mode.
DCD
Bit 3: TDCD. This bit indicates that the
pin has changed state after HSR was read by the CPU.
RI
Bit 2: FERI. This bit indicates that the
by the CPU.
pin has changed from low to high state after HSR was read
DSR
CTS
Bit 1: TDSR. This bit indicates that the
Bit 0: TCTS. This bit indicates that the
pin has changed state after HSR was read by the CPU.
pin has changed state after HSR was read.
Publication Release Date: Feb. 2002
- 51 -
Revision 0.70
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