W83697HF/F
DATA RATE
250 KB/S
300 KB/S
500 KB/S
1 MB/S
DEFAULT PRECOMPENSATION DELAYS
125 nS
125 nS
125 nS
41.67nS
20.8 nS
2 MB/S
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write current control.
RWC
00 500 KB/S (MFM), 250 KB/S (FM),
= 1
01 300 KB/S (MFM), 150 KB/S (FM), RWC = 0
10 250 KB/S (MFM), 125 KB/S (FM), RWC = 0
RWC
11 1 MB/S (MFM), Illegal (FM),
= 1
The 2 MB/S data rate for Tape drive is only supported by setting 01 to DRATE1 and DRATE0 bits, as
well as setting 10 to DRT1 and DRT0 bits which are two of the Configure Register CRF4 or CRF5 bits in
logic device 0. Please refer to the function description of CRF4 or CRF5 and data rate table for individual
data rates setting.
3.2.7
FIFO Register (R/W base address + 5)
The Data Register consists of four status registers in a stack with only one register presented to the
data bus at a time. This register stores data, commands, and parameters and provides diskette-drive
status information. Data bytes are passed through the data register to program or obtain results after a
command. In the W83697HF, this register defaults to FIFO disabled mode after reset. The FIFO can
change its value and enable its operation through the CONFIGURE command.
Publication Release Date: Feb. 2002
- 41 -
Revision 0.70
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