W83697HF/F
3.2.6
Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the
FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by
the DR REGISTER. The real data rate is determined by the most recent write to either of the DR
REGISTER or CC REGISTER.
1
7
6
5
0
4
3
2
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
1
FDC in normal mode
FDC in power-down mode
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
PRECOMP
PRECOMPENSATION DELAY
2
1
0
250K - 1 Mbps
2 Mbps Tape drive
Default Delays
20.8 nS
0
0
0
1
0
Default Delays
41.67 nS
0
0
0
1
1
1
1
0
1
1
0
0
1
1
83.34 nS
41.17 nS
1
125.00 nS
62.5nS
0
1
0
1
166.67 nS
83.3 nS
208.33 nS
104.2 nS
250.00 nS
125.00 nS
0.00 nS (disabled)
0.00 nS (disabled)
Publication Release Date: Feb. 2002
Revision 0.70
- 40 -
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