W83697HF/F
Bank 0
9.7.51 FAN 1 Duty Cycle Select Register-- 01h (
)
Power on default [7:0] 1111,1111 b
Bit
Name
F1_DC[7:0]
Read/Write
Description
7-0
Read/Write
FanPWM1 Duty Cycle. This 8-bit register determines
the number of input clock cycles, out of 256-cycle period,
during which the PWM output is high. During smart fan 1
control mode, read this register will return smart fan duty
cycle.
00h: PWM output is always logical Low.
FFh: PWM output is always logical High.
XXh: PWM output logical High percentage is
(XX/256*100%) during one cycle.
9.7.52 FAN 2 Pre-Scale Register-- Index 02h
Power on default [7:0] = 0000,0001 b
Bit
Name
Read/Write
Description
7
PWM_CLK_SEL2
Read/Write
PWM 2 Input Clock Select. This bit select Fan 2 input
clock to pre-scale divider.
0: 1 MHz
1: 125 KHz
6-0
PRE_SCALE2[6:0]
Read/Write
Fan 2 Input Clock Pre-Scale. The divider of input clock
is the number defined by pre-scale. Thus, writing 0
transfers the input clock directly to counter. The
maximum divider is 128 (7Fh).
01h : divider is 1
02h : divider is 2
03h : divider is 3
:
:
PWM frequency = (Input Clock / Pre-scale) / 256
Publication Release Date: Feb. 2002
Revision 0.70
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