W83627HF/ F/ HG/ G
TABLE B
DRVDEN0（pin 1） DRVDEN1（pin 2）
DTYPE0
DTYPE1
DRIVE TYPE
4/2/1 MB 3.5”“
2/1 MB 5.25”
0
0
SELDEN
DRATE1
DRATE0
2/1.6/1 MB 3.5” （3-MODE）
0
1
1
1
0
1
DRATE0
DRATE0
DRATE1
SELDEN
DRATE0
9.4
Logical Device 1 （Parallel Port）
CR30 （Default 0x01 if PNPCVS = 0 during POR, default 0x00 otherwise）
BIT
7 - 1
0
DESCRIPTION
Reserved.
Logic device activation control
1： Active
0： Inactived
CR60, CR 61 （Default 0x03, 0x78 if PNPCVS = 0 during POR, default 0x00, 0x00 otherwise）
These two registers select Parallel Port I/O base address.
[0x100：0xFFC] on 4 byte boundary（EPP not supported）or [0x100：0xFF8] on 8 byte bounda
（all modes supported, EPP is only available when the base address is on 8 byte boundary）.
CR70 （Default 0x07 if PNPCVS = 0 during POR, default 0x00 otherwise）
BIT
7 - 4
3 - 0
DESCRIPTION
Reserved.
These bits select IRQ resource for Parallel Port.
CR74 （Default 0x04）
BIT
DESCRIPTION
7 - 3
2 - 0
Reserved.
These bits select DRQ resource for Parallel Port.
000： DMA0
001： DMA1
010： DMA2
011： DMA3
100 ~ 111： No DMA active
Publication Release Date: June 09, 2006
Revision 2.27
- 91 -
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