W83195WG-382/W83195CG-382
STEPLESS FOR ATI K8 CLOCK GENERATOR
3. PIN CONFIGURATION
1
2
3
4
5
6
7
8
XIN
XOUT
VDD48
VDDREF
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
&FSA/REF0
&FSB/REF1
&FSC/REF2
VDDPCI
PCICLK0
GND
*TURBO_SEL/USB_48
GND
*PD#
SCLK
SDATA
9
RESET#
&CLKREQA#
&TURBO/&CLKREQB#
SRCT7
VDDHTT
HTTCLK0
GND
CPUCLK8T0
CPUCLK8C0
VDDCPU
GND
CPUCLK8T1
CPUCLK8C1
VDDA
GNDA
IREF
GND
VDDSRC
SRCT0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SRCC7
VDDSRC
GND
SRCT6
SRCC6
SRCT5
SRCC5
GND
VDDSRC
SRCT4
SRCC4
SRCT3
SRCC3
GND
ATIGT1
ATIGC1
SRCC0
VDDATI
GND
ATIGT0
ATIGC0
#: Active low
*: Internal pull up resistor 120K to VDD
&: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
2
2
A T IG T 0:1
A T IG C 0:1
D ivid er
D ivid er
A T IG L O O P
U S B L O O P
C P U L O O P
S p read
&
S yn c
48M H z
S p ectru m
3
3
X IN
X O U T
X T A L
O S C
R E F 0:2
C P U C L K 8T 0:1
C P U C L K 8C 0:1
3
S R C L O O P
S p read
V C O C L K
S p ectru m
6
D ivid e r
S R C T 0,3:7
S R C C 0,3 :7
M /N /R atio
R O M
&
S n yc
6
F S (A :C )
C R #_(A :B )
H T T C L K 0
P C I0
L atch
& P O R
*T U R B O _ S E L
& T U R B O
*P D #
C o n tro l
L o g ic
& C o n fig
R eg ister
R E S E T #
475
S D A T A
S C L K
I2C
In terfa ce
Publication Release Date: Feb 2006
Revision 0.6
- 2 -
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