Preliminary W78E378/W78C378/W78C374
Interrupts
The five interrupt sources are listed as below.
SOURCE VECTOR ADDRESS
DESCRIPTON
PRIORITY WITHIN A LEVEL
1
2
3
4
5
IE0
TF0
0003H
000BH
0013H
001BH
002BH
Interrupt 0 edge detected
Timer 0 overflow
Miscellaneous interrupts*1
Highest
IE1
TF1
Timer 1 overflow
SI1+SI2
SIO1 or SIO2 interrupt
Lowest
Note: *1: SCLINT + ADCINT + DDC1INT + SOAINT + VEVENT + PARAINT.
The miscellaneous interrupts at vector address 0013H is driven by the following six sources, which
are:
(1) SCLINT: when high-to-low transition on SCL-pin,
(2) ADCINT: when A-to-D conversion completion,
IN
(3) DDC1INT: when DDC1 data byte transmitted (after 9 clock pulses from V ) in the DDC port,
(4) SOAINT: when SOA activated,
(5) VEVENT: on every Vsync pulse or vertical frequency counter overflow,
(6) PARAINT: when parabola timer timeout.
If IE1 interrupt occurs, it is necessary for the programmer to read the INTVECT register to tell where
the interrupt request comes. These sources can be masked individually by clearing their
corresponding bits in the INTMSK register. To clear any of these interrupt flags, just write a '1' to the
corresponding bit in the INTCLR.
The interrupt enable bits and priority control bits for these five main sources are listed as below.
INTERRUPT FLAG
ENABLE BIT
IE.0 & IE.7
IE.1 & IE.7
IE.2 & IE.7
IE.3 & IE.7
IE.5 & IE.7
PRIORITY CONTROL BIT
1
2
3
4
5
IE0
TF0
IP.0
IP.1
IP.2
IP.3
IP.5
IE1
TF1
SI+SI2
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