Preliminary W78E378/W78C378/W78C374
Sync Processor
Polarity Detector
The H/V polarity is detected automatically and can be known from HPOL bit (HFCOUNTH.7) and
VPOL bit (VFCOUNTH.7).
Fosc
10 MHz
(64/Fosc) 62 (counter overflow) = 396.8 S
Max. H+V width
Max. V width
´
m
´
m
(2048/Fosc) 2 = 409.6 S
Sync Separator
The Vsync is separated from the composite sync automatically, without any software effort.
Fosc
10 MHz
Min. V width & Max. H width
´
m
(1/Fosc) 64 = 6.4 S
Horizontal & Vertical Frequency Counter
There are two 12-bit counters which can count H and V frequency automatically. When VEVENT
(Vsync frequency counter timeout) interrupt happens, the count value values are latched into the
counter registers (HFCOUNTH, HFCOUNTL, VFCOUNTH and VFCOUNTL). And then the S/W may
read the count value (HCOUNT and VCOUNT) from the counter registers to calculate the H and V
frequency by the formulas listed below.
V frequency:
RESOL
RESOL
´
The resolution of V frequency counter: V
= (1/Fosc) 64.
FREQ
COUNT
´
= 1/(V
The V frequency: V
V
).
The lowest V frequency can be detected: Fosc ÷ 262144. (38.1Hz @Fosc =10 MHz)
H frequency:
RESOL
The resolution of H frequency counter: H
= (1/Fosc) ¸ 8.
FREQ
The H frequency: H
COUNT
= 1/(H
RESOL
H ).
´
¸
The lowest H frequency can be detected: Fosc 512. (19.5 KHz @Fosc = 10 MHz)
Dummy Frequency Generator
The Dummy H and V frequencies are generated for factory burn-in or showing warning message
while there are no input frequency.
(HDUMS1, HDUMS0)
(0, 0)
(0, 1)
(1, 0)
(1, 1)
dummyH
F
´
´
´
´
´
´
´
´
5
Fosc/(8
4
8) Fosc/(8
2
8)
Fosc/(8
3
8)
Fosc/(8
8)
Hsync width
´
´
´
´
(8 4)/Fosc
(8 2)/Fosc
(8 3)/Fosc
(8 5)/Fosc
VDUMS
0
1
dummyV
F
dummyH
dummyH
F /1024
F
/ 512
dummyH
8/ F
dummyH
Vsync width
16/ F
Publication Release Date: December 1999
Revision A1
- 27 -
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