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W25Q128BV 参数 Datasheet PDF下载

W25Q128BV图片预览
型号: W25Q128BV
PDF下载: 下载PDF文件 查看货源
内容描述: 具有双路和四路SPI 3V 128M位串行闪存 [3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI]
分类和应用: 闪存
文件页数/大小: 74 页 / 756 K
品牌: WINBOND [ WINBOND ]
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W25Q128BV  
7.2.27 Erase / Program Suspend (75h)  
The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase  
operation or a Page Program operation and then read from or program/erase data to, any other sectors or  
blocks. The Erase/Program Suspend instruction sequence is shown in Figure 25.  
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not  
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If  
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status  
Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program  
Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation.  
The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the  
Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page  
Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend  
instruction will be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics) is required  
to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to  
0 within “tSUS” and the SUS bit in the Status Register will be set from 0 to 1 immediately after  
Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the  
Suspend instruction “75h” is not issued earlier than a minimum of time of “tSUS” following the preceding  
Resume instruction “7Ah”.  
Unexpected power off during the Erase/Program suspend state will reset the device and release the  
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block  
that was being suspended may become corrupted. When the device is powered up again, it is  
recommended for the user to repeat the same Erase or Program operation that was interrupted, at the  
same address location, to avoid the potention data corruption.  
/CS  
tSUS  
Mode 3  
Mode 0  
0
1
2
3
4
5
6
7
Mode 3  
Mode 0  
CLK  
Instruction (75h)  
High Impedance  
DI  
(IO0)  
DO  
(IO1)  
Accept instructions  
Figure 25. Erase/Program Suspend Instruction Sequence  
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