W25M02GV
8.2.26 Fast Read Quad I/O with 4-Byte Address (ECh)
The Fast Read Quad I/O (ECh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 prior to the data
output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code
execution (XIP) directly from the Quad SPI.
The Fast Read Quad Output instruction sequence is shown in Figure 29a & 29b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be
following and continues through the entire memory array. This allows using a single Read instruction to
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory
command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
Mode 0
0
7
8
9
10 11 12
21 22 23 24 25 25 27 28
CLK
10 Dummy
Clocks
Column
Address[15:0]
Instruction
DI
(IO0)
12
13
8
4
5
6
7
0
1
2
3
X
X
X
X
X
X
X
X
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
ECh
High Impedance
High Impedance
High Impedance
DO
(IO1)
9
14 10
15 11
IO2
IO3
7
7
7
7
*
*
*
*
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
= MSB
*
Figure 29a. Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
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