W25M02GV
ECC Status
Descriptions
ECC-1
ECC-0
0
0
Entire data output is successful, without any ECC correction.
Entire data output is successful, with 1~4 bit/page ECC corrections in either a
single page or multiple pages.
0
1
Entire data output contains more than 4 bits errors only in a single page
which cannot be repaired by ECC.
In the Continuous Read Mode, an additional command can be used to read out
the Page Address (PA) which had the errors.
1
1
0
Entire data output contains more than 4 bits errors/page in multiple pages.
In the Continuous Read Mode, the additional command can only provide the
last Page Address (PA) that had failures, the user cannot obtain the PAs for
other failure pages. Data is not suitable to use.
1
Notes:
1. ECC-1,ECC-0 = (1,1) is only applicable during Continuous Read operation (BUF=0).
7.3.3 Program/Erase Failure (P-FAIL, E-FAIL) – Status Only
The Program/Erase Failure Bits are used to indicate whether the internally-controlled Program/Erase
operation was executed successfully or not. These bits will also be set respectively when the Program or
Erase command is issued to a locked or protected memory array or OTP area. Both bits will be cleared at
the beginning of the Program Execute or Block Erase instructions as well as the device RESET
instruction.
7.3.4 Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Program
Execute, Block Erase, Page Data Read and Program Execute for OTP pages.
7.3.5 Erase/Program In Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is powering up or
executing a Page Data Read, BBM Management, Program Execute, Block Erase, Program Execute for
OTP area, OTP Locking or after a Continuous Read instruction. During this time the device will ignore
further instructions except for the Read Status Register and Read JEDEC ID instructions. When the
program, erase or write status register instruction has completed, the BUSY bit will be cleared to a 0 state
indicating the device is ready for further instructions.
7.3.6 Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be
written as “0”, but there will not be any effects.
Publication Release Date: July 1, 2015
- 20 -
Preliminary - Revision B
WINBOND [ WINBOND ]
