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25M02GVTCIG 参数 Datasheet PDF下载

25M02GVTCIG图片预览
型号: 25M02GVTCIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS]
分类和应用:
文件页数/大小: 68 页 / 820 K
品牌: WINBOND [ WINBOND ]
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W25M02GV  
4.4 Write Protect (/WP)  
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in  
conjunction with the Status Register’s Block Protect bits BP[3:0] and Status Register Protect SRP bits  
SRP[1:0], a portion as small as 256K-Byte (2x128KB blocks) or up to the entire memory array can be  
hardware protected. The WP-E bit in the Protection Register (SR-1) controls the functions of the /WP pin.  
When WP-E=0, the device is in the Software Protection mode that only SR-1 can be protected. The /WP  
pin functions as a data I/O pin for the Quad SPI operations, as well as an active low input pin for the Write  
Protection function for SR-1. Refer to section 7.1.3 for detail information.  
When WP-E=1, the device is in the Hardware Protection mode that /WP becomes a dedicated active low  
input pin for the Write Protection of the entire device. If /WP is tied to GND, all “Write/Program/Erase”  
functions are disabled. The entire device (including all registers, memory array, OTP pages) will become  
read-only. Quad SPI read operations are also disabled when WP-E is set to 1.  
4.5 HOLD (/HOLD)  
During Standard and Dual SPI operations, the /HOLD pin allows the device to be paused while it is actively  
selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals  
on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can  
resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The  
/HOLD pin is active low.  
When a Quad SPI Read/Buffer Load command is issued, /HOLD pin will become a data I/O pin for the  
Quad operations and no HOLD function is available until the current Quad operation finishes.  
4.6 Serial Clock (CLK)  
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI  
Operations")  
Publication Release Date: July 1, 2015  
- 10 -  
Preliminary - Revision B