WCMB2016R4X
Switching Characteristics
Over the Operating Range
WCMB2016R4X
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z
BLE / BHE HIGH to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
10
70
60
60
0
0
50
60
30
0
25
5
25
0
70
70
10
25
5
25
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
WRITE CYCLE
Note:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels of 0 to V
CC(typ)
, and
output loading of the specified I
OL
/I
OH
and 30 pF load capacitance.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than
t
LZWE
for any given device.
10. t
HZOE
, t
HZCE
, t
HZBE
and t
HZWE
transitions are measured when the outputs enter a high impedence state.
11. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE =V
IL
. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be
referenced to the edge of the signal that terminates the write.
5
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
