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WED3EG72M18S265JD3SG 参数 Datasheet PDF下载

WED3EG72M18S265JD3SG图片预览
型号: WED3EG72M18S265JD3SG
PDF下载: 下载PDF文件 查看货源
内容描述: 128MB - 16Mx72 DDR SDRAM UNBUFFERED [128MB - 16Mx72 DDR SDRAM UNBUFFERED]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 12 页 / 197 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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WED3EG7218S-JD3  
White Electronic Designs  
PRELIMINARY  
ICC SPECIFICATIONS AND TEST CONDITIONS  
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V includes DDR SDRAM component only  
DDR266@  
CL=2  
Max  
DDR266@  
CL=2.5  
Max  
DDR200@  
CL=2  
Max  
DDR400@  
CL=3  
Max  
DDR333@  
CL=2.5  
Max  
Parameter  
Symbol Conditions  
One device bank; Active =  
Units  
Precharge; TRC=TRC(MIN);  
TCK=TCK(MIN); DQ,DM and DQS  
inputs changing once per clock cycle;  
Address and control inputs changing  
once every two cycles  
Operating  
Current  
ICC0  
990  
990  
810  
mA  
One device bank; Active-read-  
Precharge; Burst = 2; TRC=TRC(MIN);  
TCK=TCK(MIN); lout=0mA; Address  
and control inputs changing once per  
clock cycle  
Operating  
Current  
ICC1  
1260  
270  
1260  
270  
1035  
255  
mA  
mA  
Precharge  
Power-Down  
Standby  
All device banks idle; Power-down  
mode; TCK=TCK(MIN); CKE=(low)  
ICC2P  
Current  
CS# = High; All device banks idle;  
TCK=TCK(MIN); CKE=high; Address  
and other control inputs changing  
once per clock cycle. VIN = VREF for  
DQ, DQS and DM.  
Idle Standby  
Current  
ICC2F  
495  
315  
495  
315  
405  
270  
mA  
mA  
Active Power-  
Down Standby  
Current  
One device bank active; Power-down  
mode; TCK(MIN); CKE=(low)  
ICC3P  
CS# = High; CKE = High; One  
device bank; Active-Precharge; TRC  
= TRAS(MAX); TCK = TCK(MIN); DQ,  
DM and DQS inputs changing twice  
per clock cycle; Address and other  
control inputs changing once per  
clock cycle.  
Active Standby  
Current  
ICC3N  
540  
540  
450  
mA  
Burst = 2; Reads; Continous burst;  
One device bank active; Address  
and control inputs changing once per  
clock cycle;  
Operating  
Current  
ICC4R  
1800  
1800  
1485  
mA  
mA  
TCK = TCK(MIN); lout = 0mA  
Burst = 2; Writes; Continous burst;  
One device bank active; Address  
and control inputs changing once per  
clock cycle; TCK = TCK(MIN); DQ, DM  
and DQS inputs changing twice per  
clock cycle.  
Operating  
Current  
ICC4W  
1935  
1935  
1935  
1935  
1530  
1530  
Auto Refresh  
Current  
ICC5  
TRC = TRC(MIN)  
mA  
mA  
Standard  
CKE ≤ 0.2V  
18  
9
18  
9
18  
9
Self Refresh  
Current  
ICC6  
Low Power  
June 2006  
Rev. 2  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com