WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
335
262/265
Min Max
-0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75
202
Parameter
Symbol Min
tAC
tCH
Max
Min
Max
Min
Max
Units Notes
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
ns
0.45
0.45
5
0.55
0.55
7.5
13
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
16
16
tCL
Clock cycle time
CL=3
tCK (3)
22
CL=2.5 tCK (2.5)
6
6
13
13
7.5
7.5
13
13
7.5
10
13
13
22
CL=2
tCK (2)
tDH
7.5
0.40
0.40
1.75
13
7.5
22
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
0.45
0.45
1.75
0.5
0.5
0.5
1.75
14,17
14,17
17
tDS
0.5
tDIPW
1.75
tDQSCK -0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75
tDQSH
tDQSL
tDQSQ
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
0.40
1.28
0.45
1.25
0.5
0.5
13,14
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tDQSS
tDSS
tDSH
tHP
0.72
0.2
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.2
0.2
0.2
0.2
tCH, tCL
tCH, tCL
tCH, tCL
tCH, tCL
18
8,19
8,20
6
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
tHZ
+0.70
+0.70
+0.75
+0.75
tLZ
-0.70
0.60
0.60
0.60
0.60
2.2
-0.70
0.75
0.75
0.80
0.80
2.2
-0.75
0.90
0.90
1
-0.75
0.90
0.90
1
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
tIHf
tISf
6
tIHs
6
tISs
1
1
6
tIPW
tMRD
2.2
2.2
10
12
15
15
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
13,14
15
Data hold skew factor
tQHS
0.50
0.55
0.75
0.75
ns
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
tRAS
tRAP
tRC
40
15
55
70
70,000
42
15
60
72
70,000
40 120,000 45 120,000 ns
15
60
75
20
65
75
ns
ns
ns
tRFC
21
June 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
