WED3EG7218S-JD3
White Electronic Designs
PRELIMINARY*
128MB – 16Mx72 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
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Double-data-rate architecture
The WED3EG7218S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
component. The module consists of nine 16Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
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DDR200, DDR266, DDR333 and DDR400
• JEDEC design specified
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BI-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Serial presence detect
Power supply:
•
•
V
CC = VCCQ = 2.5V±0.2V
(100, 133 and 166MHz)
CC = VCCQ = 2.6V±0.1V
(200MHz)
V
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JEDEC 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") Max
NOTE: Consult factory for availability of:
• RoHS Products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR400 @CL=3
DDR333 @CL=2.5
166MHz
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
200MHz
3-3-3
2.5-3-3
2-2-2
2.5-3-3
2-2-2
June 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
