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WED2ZLRSP01S50BC 参数 Datasheet PDF下载

WED2ZLRSP01S50BC图片预览
型号: WED2ZLRSP01S50BC
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32 / 256K ×32双阵列同步管道突发式SRAM NBL [512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM]
分类和应用: 静态存储器
文件页数/大小: 13 页 / 350 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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WED2ZLRSP01S  
White Electronic Designs  
FIG. 3 TIMING WAVEFORM OF READ CYCLE  
tCH  
tCL  
Clock  
tCYC  
tCES  
tCEH  
CKE#  
tAS  
tAH  
A1  
A2  
A3  
Address  
WRITE#  
tWH  
tWS  
tCSS  
tCSH  
CEx#  
tADVS  
tADVH  
ADV  
OE#  
tCD  
tOH  
tOE  
tLZOE  
tHZOE  
tHZC  
Q1-1  
Q3-2  
Q3-3  
Q3-4  
Q2-1  
Q2-2  
Q2-3  
Q3-1  
Q2-4  
Data Out  
Dont Care  
Undefined  
NOTES:  
WRITE# = L means WE# = L, and BWx# = L  
CEx# refers to the combination of CE1#, CE2 and CE2#.  
Note:  
Applies to both independent arrays.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
April, 2002  
Rev. 0  
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com