WED2ZLRSP01S
White Electronic Designs
AC CHARACTERISTICS
166MHz
150MHz
133MHz
100MHz
Units
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Clock Time
Clock Access Time
tCYC
tCD
tOE
tLZC
tOH
tLZOE
tHZOE
tHZC
tCH
tCL
tAS
tCES
tDS
tWS
tADVS
tCSS
tAH
tCEH
tDH
tWH
tADVH
tCSH
6.0
—
—
1.5
1.5
0.0
—
6.7
—
—
1.5
1.5
0.0
—
7.5
—
—
1.5
1.5
0.0
—
10.0
—
—
1.5
1.5
0.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.5
3.5
—
—
—
3.0
3.0
—
—
—
3.8
3.8
—
—
—
3.0
3.0
—
—
—
4.2
4.2
—
—
—
3.5
3.5
—
—
—
5.0
5.0
—
—
—
3.5
3.5
—
—
—
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
—
—
—
—
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Clock Low Pulse Width
Address Setup to Clock High
CKE# Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE# Hold to Clock High
Data Hold to Clock High
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is
sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low.
Both cases must meet setup and hold times.
4. Applies to each of the independent arrays.
AC TEST CONDITIONS
(0 ≤ TA ≤ 70°C, VCC = 2.5V 5ꢀ, Unless Otherwise Specified)
Parameter
Input Pulse Level
Value
0 to 2.5V
Input Rise and Fall Time (Measured at 20ꢀ to 80ꢀ)
Input and Output Timing Reference Levels
Output Load
1.0V/ns
1.25V
See Output Load (A)
OUTPUT LOAD (A)
OUTPUT LOAD (B)
(for tLZC, tLZOE, tHZOE, and tHZC
)
Dout
RL=50Ω
VL=1.25V
+2.5V
30pF*
Zo=50Ω
1667Ω
Dout
1538Ω
5pF*
*Including Scope and Jig Capacitance
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
