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WED2ZLRSP01S50BC 参数 Datasheet PDF下载

WED2ZLRSP01S50BC图片预览
型号: WED2ZLRSP01S50BC
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32 / 256K ×32双阵列同步管道突发式SRAM NBL [512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM]
分类和应用: 静态存储器
文件页数/大小: 13 页 / 350 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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WED2ZLRSP01S  
White Electronic Designs  
ABSOLUTE MAXIMUM RATINGS*  
Voltage on Vdd Supply Relative to VSS  
-0.3V to +3.6V  
V
IN (DQx)  
-0.3V to +3.6V  
-0.3V to +3.6V  
-55°C to +125°C  
100mA  
VIN (Inputs)  
Storage Temperature (BGA)  
Short Circuit Output Current  
*Stress greater than those listed under “Absolute Maximum Ratings”: may cause permanent damage to the device. This is a stress rating  
only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this  
specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.  
ELECTRICAL CHARACTERISTICS (0°C ≤ TA ≤ 70°C)  
Description  
Symbol  
VIH  
VIL  
ILI  
ILO  
VOH  
VOL  
VCC  
Conditions  
Min  
1.7  
-0.3  
-5  
-5  
2.0  
---  
Max  
VCC +0.3  
0.7  
5
5
---  
0.4  
Units  
V
V
µA  
µA  
V
Notes  
Input High (Logic 1) Voltage  
Input Low (Logic 0) Voltage  
Input Leakage Current  
Output Leakage Current  
Output High Voltage  
Output Low Voltage  
Supply Voltage  
1
1
2
0V ≤ VIN ≤ VCC  
Output(s) Disabled, 0V ≤ VIN ≤ VCC  
IOH = -1.0mA  
1
1
1
IOL = 1.0mA  
V
V
2.375  
2.625  
NOTES:  
1. All voltages referenced to VSS (GND)  
2. ZZ pin has an internal pull-up, and input leakage is higher.  
DC CHARACTERISTICS  
166  
MHz  
150  
MHz  
133  
MHz  
100  
MHz  
Description  
Symbol Conditions  
Typ  
Units Notes  
Power Supply  
Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle  
Time = tCYC MIN; VCC = MAX; Output Open  
Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2  
or VCC - 0.2; All Inputs Static; CK Frequency = 0;  
ZZ ≤ VIL  
Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle  
Time =tCYC MIN; VCC = MAX; Output Open;  
ZZ ≥ VCC - 0.2V  
Device Deselected; VCC = MAX; All Inputs  
≤ VSS + 0.2 or VCC - 0.2; Cycle Time = tCYC  
MIN; ZZ ≤ VIL  
IDD  
650  
600  
560  
500  
60  
mA  
mA  
1, 2  
2
Current: Operating  
Power Supply  
Current: Standby  
ISB2  
30  
20  
60  
40  
60  
40  
60  
40  
Power Supply  
Current: Current  
ISB3  
40  
80  
mA  
mA  
2
2
Clock Running  
Standby Current  
ISB4  
140  
120  
100  
NOTES:  
1.  
IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading.  
2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time.  
BGA CAPACITANCE  
Description  
Symbol  
CI  
CO  
CA  
CCK  
Conditions  
Typ  
Max  
Units  
pF  
pF  
pF  
pF  
Notes  
Control Input Capacitance  
Input/Output Capacitance (DQ)  
Address Capacitance  
Clock Capacitance  
TA = 25°C; f = 1MHZ  
TA = 25°C; f = 1MHZ  
TA = 25°C; f = 1MHZ  
TA = 25°C; f = 1MHZ  
5
6
5
3
7
8
7
5
1
1
1
1
NOTES:  
1. This parameter is sampled.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
April, 2002  
Rev. 0  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com