W764M32V-XSBX
White Electronic Designs
ADVANCED*
FIGURE 10: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
tAHT
tAS
Addresses
tAHT
tASO
CS#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
tOE
Valid
Data
Valid
Status
Valid
Valid
Valid Data
DQ6/DQ2
Status
Status
(Stops Toggling)
(First Read)
(Second Read)
RY/BY#
NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
FIGURE 11: DQ2 Vs. DQ6
Enter
Erase
Enter Erase
Erase
Embedded
Erasing
Resume
Suspend Program
Suspend
Erase
Erase
Erase Suspend
Read
Erase
Erase Suspend
Read
Erase
WE#
Complete
Suspend
Program
DQ6
DQ2
NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CS# to toggle DQ2 and DQ6.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 2
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
