W764M32V-XSBX
White Electronic Designs
ADVANCED*
FIGURE 9: DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
tRC
Addresses
CS#
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Complement
True
True
Valid Data
Complement
Status Data
Valid Data
Status Data
DQ0-DQ6
tBUSY
RY/BY#
NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com