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W3E32M72S-266BI 参数 Datasheet PDF下载

W3E32M72S-266BI图片预览
型号: W3E32M72S-266BI
PDF下载: 下载PDF文件 查看货源
内容描述: 32Mx72 DDR SDRAM [32Mx72 DDR SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 19 页 / 669 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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W3E32M72S-XBX  
White Electronic Designs  
47. Random addressing changing: 50% of data changing at every transfer.  
48. Random addressing changing: 100% of data changing at every transfer.  
49. CKE must be active (high) during the entire time a refresh command is executed.  
That is, from the time the AUTO REFRESH command is registered, CKE must be  
active at each rising clock edge, until tRFC has been satisfied.  
50.  
ICC2N specifies the DQ, DQS, and DQM to be driven to a valid high or low logic  
level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and control inputs  
to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.”  
51. Whenever the operating frequency is altered, not including ꢀitter, the DLL is  
required to be reset followed by 200 clock cycles before any READ command.  
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20  
MHz. Any noise above 20 MHz at the DRAM generated from any source other than  
that of the DRAM itself may not exceed the DC coltage range of 2.6V 100mV.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
March 2006  
Rev. 2  
16  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com