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W3E32M72S-266BI 参数 Datasheet PDF下载

W3E32M72S-266BI图片预览
型号: W3E32M72S-266BI
PDF下载: 下载PDF文件 查看货源
内容描述: 32Mx72 DDR SDRAM [32Mx72 DDR SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 19 页 / 669 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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W3E32M72S-XBX  
White Electronic Designs  
NOTES:  
14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew  
rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per  
each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that  
is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.  
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at  
which CK# and CK# cross; the input reference level for signals other than CK/CK#  
1. All voltages referenced to VSS.  
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be  
conducted at nominal reference/supply voltage levels, but the related specifications  
and device operation are guaranteed for the full voltage range specified.  
3. Outputs measured with equivalent load:  
V
TT  
is VREF  
.
16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including  
SELF REFRESH mode, VREF must be powered within specified range. Exception:  
during the period before VREF stabilizes, CKE 0.3 x VCCQ is recognized as LOW.  
17. The output timing reference level, as measured at the timing reference point  
indicated in Note 3, is VTT.  
50Ω  
Reference  
Output  
(VOUT  
Point  
30pF  
)
18.  
tHZ and tLZ transitions occur in the same access time windows as valid data  
transitions. These parameters are not referenced to a specific voltage level, but  
specify when the device output is no longer driving (HZ) or begins driving (LZ).  
19. The intent of the Don't Care state after completion of the postamble is the DQS-  
driven signal should either be high, low, or high-Z and that any signal transition  
within the input switching region must follow valid input requirements. That is, if  
DQS transitions high (above VIHDC(MIN) then it must not transition low (below  
VIHDC) prior to tDQSH(MIN).  
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test  
environment, but input timing is still referenced to VREF (or to the crossing point for  
CK/CK#), and parameter specifications are guaranteed for the specified AC input  
levels under normal use conditions. The minimum slew rate for the input signals  
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).  
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard  
(i.e., the receiver will effectively switch as a result of the signal crossing the AC  
input level, and will remain in that state as long as the signal does not ring back  
above [below] the DC input LOW [HIGH] level).  
20. This is not a device limit. The device will operate with a negative value, but system  
performance could be degraded due to bus turnaround.  
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE  
command. The case shown (DQS going from High-Z to logic LOW) applies when  
no WRITEs were previously in progress on the bus. If a previous WRITE was in  
6.  
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations  
in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may  
not exceed 2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed 25mV  
for DC error and an additional 25mV for AC noise. This measurement is to be  
taken at the nearest VREF by-pass capacitor.  
progress, DQS could be HIGH during this time, depending on tDQSS  
.
22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets  
the minimum absolute value for the respective parameter. tRAS (MAX) for ICC  
measurements is the largest multiple of tCK that meets the maximum absolute  
7.  
8.  
V
TT is not applied directly to the device. VTT is a system supply for signal  
termination resistors, is expected to be set equal to VREF and must track variations  
in the DC level of VREF  
ID is the magnitude of the difference between the input level on CK and the input  
level on CK#.  
value for tRAS  
.
.
23. The refresh period 64ms. (32ms for Military grade) This equates to an average  
refresh rate of 7.8125µs. However, an AUTO REFRESH command must be  
asserted at least once every 70.3µs; (35µs for Military grade) burst refreshing or  
posting by the DRAM controller greater than eight refresh cycles is not allowed.  
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this  
maximum amount for any given device.  
V
9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device  
and must track variations in the DC level of the same.  
10.  
I
CC is dependent on output loading and cycle rates. Specified values are obtained  
with minimum cycle time with the outputs open.  
11. Enables on-chip refresh and address counters.  
12. CC specifications are tested after the device is properly initialized, and is averaged  
25. The valid data window is derived by achieving other specifications - tHP (tCK/2),  
t
DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional  
I
with the clock duty cycle and a practical data valid window can be derived. The  
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain  
when operating beyond a 45/55 ratio. The data valid window derating curves are  
provided below for duty cycles ranging between 50/50 and 45/55.  
at the defined cycle rate.  
13. This parameter is not tested but guaranteed by design. tA = 25°C, F= 1 MHz  
FIGURE A – FULL DRIVE PULL-DOWN  
FIGURE B – FULL DRIVE PULL-UP  
CHARACTERISTICS  
CHARACTERISTICS  
160  
0
Maximum  
-20  
140  
Minimum  
-40  
120  
-60  
-80  
Nominal low  
Nominal high  
Nominal high  
100  
80  
-100  
-120  
-140  
-160  
-180  
-200  
Nominal low  
60  
Minimum  
40  
20  
0
Maximum  
0.0  
0.5  
1.0  
CCQ  
1.5  
- VOUT (V)  
2.0  
2.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
V
VOUT (V)  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
March 2006  
Rev. 2  
14  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com