Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Interleaving Column Read Cycle
Figure 14.1
(Burst Length = 4, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK1
CS
RAS
CAS
WE
DSF
BS
RBw
RBw
RAx
RAx
A9
A0 ~ A8
CBx
CBy
CBz
CAx
CBw
CAy
tAC1
tRCD
DQM
DQ
Hi-Z
Ax0
Ay1
Bz2
Ay0
Bz1
Ax1 Ax2 Ax3 Bw0 Bw1
Bz0
Bz3
Bx0 Bx1
By1
By0
Precharge
Command
Bank A
Precharge
Command
Bank B
Activate
Read
Activate
Command
Bank A
Read
Read
Read
Command
Bank B
Command
Bank B
Command
Bank B
Command
Bank A
Command
Bank B
Read
Read
Command
Bank B
Command
Bank A
Document:
Rev.1
Page28