Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 14.3. Interleaved Column Read Cycle (Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
DSF
BS
RBx
RAx
RAx
A9
CAx RBx
CBx
CBy
CBz
CAy
A0 ~ A8
t
tRCD
DQM
DQ
AC3
Hi-Z
Bx0
Bx1
Ax0
Ax1
Ax2
Ax3
By0
Ay3
Bz0
Bz1
Ay0
Ay1
By1
Ay2
Read
Read
Precharge Precharge
Command
Bank B
Read
Read
Command
Bank B
Read
Command
Bank B
Command
Bank A
Command
Bank B
Command
Bank A
Activate
Command
Command
Bank A
Bank A
Activate
Command
Bank B
Document:
Rev.1
Page30