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VG4632321AQ-7 参数 Datasheet PDF下载

VG4632321AQ-7图片预览
型号: VG4632321AQ-7
PDF下载: 下载PDF文件 查看货源
内容描述: 524,288x32x2位CMOS同步图形RAM [524,288x32x2-Bit CMOS Synchronous Graphic RAM]
分类和应用:
文件页数/大小: 81 页 / 1954 K
品牌: VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
 浏览型号VG4632321AQ-7的Datasheet PDF文件第19页浏览型号VG4632321AQ-7的Datasheet PDF文件第20页浏览型号VG4632321AQ-7的Datasheet PDF文件第21页浏览型号VG4632321AQ-7的Datasheet PDF文件第22页浏览型号VG4632321AQ-7的Datasheet PDF文件第24页浏览型号VG4632321AQ-7的Datasheet PDF文件第25页浏览型号VG4632321AQ-7的Datasheet PDF文件第26页浏览型号VG4632321AQ-7的Datasheet PDF文件第27页  
Preliminary  
VG4632321A  
524,288x32x2-Bit  
CMOS Synchronous Graphic RAM  
VIS  
Electrical Characteristics and Recommended A.C. Operating Conditions  
(V = 3.3V±0.3V, Ta = 0~70°C) (Note: 6, 7, 8, 9, 10) *** CL is CAS Latency.  
DD  
symbol  
A.C. Parameter  
-4.5  
-5  
-5.5  
-6  
-7  
unit note  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
t
t
t
Row cycle time  
55  
15  
15  
55  
15  
15  
56.5  
16.5  
16.5  
60  
18  
18  
62  
20  
20  
10  
10  
10  
RC  
RAS to CAS delay  
RCD  
RP  
Precharge to refresh/row activate  
command  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Row activate to row activate delay  
Row activate to precharge time  
Write recovery time  
9
10  
11  
12  
14  
10  
RRD  
RAS  
WR  
CK1  
CK2  
CK3  
CH  
40 100K 40 100K 40 100K 42 100K 42 100K  
7
-
7
-
7
-
7
18  
8
7
18  
9
ns  
CL* = 1  
CL* = 2  
CL* = 3  
-
-
-
Clock cycle time  
4.5  
2
5
2
2
5.5  
2
6
7
Clock high time  
Clock low time  
2
2.5  
2.5  
2
2
2
CL  
CL* = 1  
CL* = 2  
CL* = 3  
-
-
-
-
-
-
17  
6
17  
6
AC1  
AC2  
AC3  
T
Access time from CLK  
(positive edge)  
4
4.5  
10  
5
5.5  
10  
6
Transition time of CLK (Rise and Fall)  
CAS to CAS Delay time  
0.5  
1
10  
0.5  
1
0.5  
1
10  
0.5  
0.5  
10  
1
1
CLK  
CCD  
OH  
Data output hold time  
1.5  
2
2
2
2
2
Data output low impedance  
2
2
2
2
LZ  
Data output high impedance(CL = 1)  
Data output high impedance(CL = 2)  
Data output high impedance(CL = 3)  
Data/Address/Control Input setup time  
Data/Address/Control Input hold time  
Minimum CKE ”High”for Self-Refresh exit  
Power Down Exit set-up time  
-
-
-
-
-
-
-
-
-
2
5
5
5
3
6
6
5
9
HZ1  
HZ2  
HZ3  
IS  
ns  
-
-
-
2
2
3
9
2
4
2
4.5  
2
4.5  
3
9
1.5  
0.8  
1
1.5  
0.8  
1
1.5  
1
1.5  
1
2
1
IH  
1
1
1
CLK  
SRX  
PDE  
RSC  
BWC  
DAL2  
4
4
4
5
5
2
ns  
(Special) Mode Register Set Cycle time  
Block Write Cycle time  
2
2
2
2
CLK 10  
CLK  
1
1
1
1
1
Data-in to ACT (REF) Command (CL = 2)  
-
-
-
1clk+  
1clk+  
t
t
ns  
RP  
RP  
t
Data-in to ACT (REF) Command (CL = 3) 1clk+  
1clk+  
1clk+  
1clk+  
1clk+  
DAL3  
t
t
t
t
t
RP  
RP  
RP  
RP  
RP  
t
t
Block Write to Precharge command  
Refresh time  
1
1
1
1
1
CLK  
ms  
BPL  
REF  
32  
32  
32  
32  
32  
Document:  
Rev.1  
Page23  
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