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VG4632321AQ-7 参数 Datasheet PDF下载

VG4632321AQ-7图片预览
型号: VG4632321AQ-7
PDF下载: 下载PDF文件 查看货源
内容描述: 524,288x32x2位CMOS同步图形RAM [524,288x32x2-Bit CMOS Synchronous Graphic RAM]
分类和应用:
文件页数/大小: 81 页 / 1954 K
品牌: VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
 浏览型号VG4632321AQ-7的Datasheet PDF文件第20页浏览型号VG4632321AQ-7的Datasheet PDF文件第21页浏览型号VG4632321AQ-7的Datasheet PDF文件第22页浏览型号VG4632321AQ-7的Datasheet PDF文件第23页浏览型号VG4632321AQ-7的Datasheet PDF文件第25页浏览型号VG4632321AQ-7的Datasheet PDF文件第26页浏览型号VG4632321AQ-7的Datasheet PDF文件第27页浏览型号VG4632321AQ-7的Datasheet PDF文件第28页  
Preliminary  
VG4632321A  
524,288x32x2-Bit  
CMOS Synchronous Graphic RAM  
VIS  
Note:  
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device.  
2. All voltages are referenced to V  
.
SS  
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum  
value of t and t . Input signals are changed one time during t . Assume that there is only one read/write cycle  
CK  
RC  
CK  
during t (min).  
RC  
4. These parameters depend on the output loading. Specified values are obtained with the output open.  
5. Assume minimum column address update cycle t  
(min).  
CCD  
6. Power-up sequence is described in Note 11.  
7. A.C. Test Conditions  
Reference Level of Output Signals  
Output Load  
1.4V / 1.4V  
Reference to the Under Output Load (B)  
Input Signal Levels  
3.0V / 0.0V  
1ns  
Transition Time (Rise and Fall) of Input Signals  
Reference Level of Input Signals  
1.4V  
3.3V  
1.4V  
1.2KW  
50  
W
ZO=50  
W
Output  
Output  
30pF  
30pF  
870W  
LVTTL D.C. Test Load (A)  
LVTTL A.C. Test Load (B)  
8. Transition times are measured between V and V . Transition (rise and fall) of input signals are fixed slope (1 ns).  
IH  
IL  
9. t defines the time at which the outputs achieve the open circuit condition and are not reference levels.  
HZ  
10. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as  
follows:  
the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number)  
Latency relationship to frequency (Unit : clock cycles)  
-4.5 Version (Calculation with t = 4.5ns ~ 30ns)  
CK  
Clock period  
(t  
t
t
t
t
t
t
RCD  
RC  
RP  
RRD  
RAS  
RSC  
)
CK  
55ns  
15ns  
9ns  
1
40ns  
9ns  
1
15ns  
30ns  
20ns  
15ns  
10ns  
4.5ns  
2
3
1
1
1
2
4
2
2
3
4
9
1
1
1
2
4
1
1
4
1
1
6
1
1
13  
2
2
Document:  
Rev.1  
Page24  
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