Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
ADDRESS
READ
NOP
NOP
PRE
ACT
NOP
tRP
Bank a,
Row
Bank
(a or all)
Bank a,
Col n
CL=1.5
DQS
DQ
DO
n
CLK#
CLK
COMMAND
ADDRESS
READ
NOP
NOP
PRE
ACT
NOP
tRP
Bank
(a or all)
Bank a,
Row
Bank a,
Col n
CL=3
DQS
DQ
DO
n
DONT’ CARE
UNDEFINED
DO n=Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 13b
READ TO PRECHARGE - OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page37