Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
CLK#
CLK
RD/
WR
ACT
Row
COMMAND
A0-A12
NOP
NOP
NOP
NOP
ACT
Row
NOP
Col
BA0,BA1
Bank x
Bank y
Bank y
tRCD
tRRD
DONT’ CARE
Figure 5
tRCD AND tRRD Definition
READs
READ bursts are initiated with a READ command, as shown in Figure 6.
The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is
either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being accessed is pre-
charged at the completion of the burst. For the generic READ commands used in the following illustrations, AUTO
PRECHARGE is disabled.
During READ bursts, the valid data-out element from the starting column address will be available following the
CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next pos-
itive or negative clock edge (i.e. at the next crossing of CLK and CLK#). Figure 7 shows general timing for each
posible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on
DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read
postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z.
Data fom any READ burst may be concatenated with or truncated with data from a subsequent READ com-
mand. In either case, a continuous flow of data can be maintained. The first data element from the new burst fol-
low either the last element of a completed burst or the last desired data element of a longer burst which is being
truncated. The new READ command should be issued x cycles after the first READ command, where x equals the
number of desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown in Figure
8. A READ command can be initiated on any clock cycle following a previous READ command. Non consecutive
READ data is shown for illustration in figure 9. Full-speed random read accesses within a page (or pages) can be
performed as shown in Figure 10.
Document : 1G5-0157
Rev.1
Page21
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
