Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the DDR SDRAM.
The DDR SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an DDR SDRAM which is selected
(CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Opera-
tions already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0-A12 See mode register descriptions in the Register Defini-
tion section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a sub-
sequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank . A
PRECHARGE command must be issued befor opening a different row in the same bank.
READ
The READ command is used to initaiate a burst read access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on inputs A0-Ai(where i=8 for x 16, 9 for x8 or 11 for x 4,
except A10) selects the starting column location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the
end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent
accesses.
WRITE
The WRITE command is used to initaiate a burst write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided on inputs A0-Ai(where i=8 for x 16, 9 for 8 or 11 for x
4, except A10) selects the starting column location. The value on input A10 determines whether or not
AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be pre-
charged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM
input logic level appearing coincident whith the data. If a given DM signal is registered LOW, the corre-
sponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that byte/column location.
Document : 1G5-0157
Rev.1
Page17
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
