Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRE-
CHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in
the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1
are treated as “Dont’ Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same individual-bank precharge function described
above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRE-
CHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically performed upon completion of the READ or
WRITE burst. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual
READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The
user must not issue another command to the same bank until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described
for each burst type in the Operation section of this data sheet.
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with autoprecharge disabled). The
most recently registered READ command prior to the BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analagous to CAS#
BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be
issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address bits a “Dont’ Care”
during an AUTO REFRESH command. The 256Mb DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 7.81ms(maximum).
Document : 1G5-0157
Rev.1
Page18
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
