Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Interleaved Column Read Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS
RAS
CAS
WE
BS
Ra
Ra
Ra
Ra
A10
Ca
Cb
Cc
Cb
Ca
ADD
DQM
t
t
RCD
RRD
t
AC3
Hi-Z
QBa0
QBb0
QBc0
QAb0
QBc1 QAb1 QAb2 QAb3
QAa3
QBa1
Read
QBb1
Read
DQ
QAa1
Read
QAa0
QAa2
Activate
Command
Bank A
Read
Command
Bank A
Read
Precharge
Command
Bank B
Precharge
Command
Bank A
Command
Command
Command
Bank B
Command
Bank B
Bank A
Bank B
(Bank D)
(Bank D) (Bank D)
(Bank D)
Activate
Command
Bank B
(Bank D)
Document : 1G5-0153
Rev.1
Page53