Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Random Row Write (Interleaving Banks) (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK
High
CS
RAS
CAS
WE
BS
A10
RBa
ADD
t
t
t
t
DQM
RCD
DPL
DPL
RP
Hi-Z
QAa4
QAa3
QAa5 QAa6 QAa7 QBa0 QBa1
QAb1
QAb2 QAb3
QBb7 QAb0
QAa0 QAa1
QBa2 QBa3
QBa5 QBa6
QBa4
QAa2
DQ
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank B
(Bank D)
Activate
Write
Command
Bank A
Command
Bank B
(Bank D)
(Bank D)
Document : 1G5-0153
Rev.1
Page49