Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Interleaved Column Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK
CKE
CS
RAS
CAS
WE
BS
Ra
Ra
Ra
Ra
A10
Ca
Cb
Cc
Cb
Ca
Cd
ADD
t
t
t
t
RCD
DPL
DPL
DQM
t
RRD
RP
Hi-Z
QBa0 QBa1 QBb0
QBc0 QBc1 QAb0
QAb1 QBd0 QBd1 QBd2 QBd3
QAa3
QBb1
DQ
QAa0 QAa1
QAa2
Write
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank A
Write
Write
Precharge
Write
Command
Command
Command
Command
Command
Bank B
(Bank D)
Bank B
Bank B
Bank B
Bank B
(Bank D)
(Bank D)
(Bank D)
(Bank D)
Activate
Command
Bank B
Precharge
Command
Bank A
(Bank D)
Document : 1G5-0153
Rev.1
Page55
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
