Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
7.Precharge
The precharge command can be asserted anytime after t
is satisfied.
RAS(min)
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM
enters the idle state after t is satisfied. The parameter t is the time required to perform the precharge.
RP(min.)
RP
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is
as follows.
Burst lengh=4
T7
PrechargeE
T0
T1
T3
T6
T2
T4
T5
CLK
Command
Read
PRE
Q2
CAS latency = 2
Hi - Z
DQ
Q0
Q1
Q3
Command
CAS latency = 3
DQ
Read
PRE
Q1
Hi - Z
Q3
Q2
Q0
CAS latency = 2 : One clock earlier than the last output data.
3 : Two clocks earlier than the last output data.
(tRAS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter ”tDPL” must be satis-
fied. The tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The
minimum number of clocks can be calculated by dividing tDPL(min.) by the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the
last data word is valid. In the following table, minus means clocks before the reference; plus means time
after the reference.
CAS latency
2
Read
-1
Write
+ tDPL(min.)
3
-2
+ tDPL(min.)
Document : 1G5-0153
Rev.1
Page17
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
