Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
Note
2.5 Command Truth Table for CKE
1
Current state
CKE CKE CS RAS CAS
WE
Address
Action
Notes
n - 1
n
Self refresh
(S.R.)
H
L
L
L
L
L
H
X
H
H
H
H
L
X
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID, CLK (n - 1)would exit S.R.
S.R. Recovery
S.R. Recovery
ILLEGAL
2
2
L
L
X
X
X
ILLEGAL
X
H
X
X
Maintain S.R.
Self refresh
recovery
H
Idle after tRC
H
H
L
H
H
X
X
Idle after tRC
H
H
H
H
H
H
L
H
H
L
L
L
H
L
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
H
L
X
H
H
L
Begin clock suspend next cycle
Begin clock suspend next cycle
ILLEGAL
5
5
L
L
L
L
L
X
X
X
X
X
ILLEGAL
H
L
X
X
X
X
X
X
X
X
Exit clock suspend next cycle
Maintain clock suspend
INVALID, CLK (n - 1) would exit P.D.
2
2
L
Power down
(P.D.)
H
L
X
H
X
X
EXIT P.D.® Idle
Maintain power down mode
L
L
X
H
X
X
X
X
X
X
Both banks
idle
H
H
Refer to operations in Operative
Command Table
H
H
H
H
L
L
H
L
X
H
X
X
Refer to operations in Operative
Command Table
Refer to operation in Operative
Command Table
H
H
H
H
L
L
L
L
L
L
H
L
X
Auto Refresh
Op - Code Refer to operations in Operative
Command Table
H
H
H
L
L
L
H
L
L
X
H
L
X
X
H
X
X
X
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
Refer to operations in Operative
Command Table
H
H
L
L
L
L
L
L
L
L
H
L
X
Self refresh
3
Op - Code Refer to operations in Operative
Command Table
L
X
H
X
X
X
X
X
X
X
X
X
X
Power down
3
4
Any state
other than
listed above
H
Refer to operations in Operative
Command Table
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
Note:
1. H : Hight level, L : low level, X : High or low level (Don't care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.
Document : 1G5-0153
Rev.1
Page13
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
