Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
VIS
6.Address Bits of Bank-Select and Precharge
6.1 Quad banks controlled by A12 & A13 (for VG36648041/VG36648042)
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
(Activate command)
Row
A12
0
A13 Result
0
1
0
1
Select Bank A
“Activate “ command
0
1
1
Select Bank B
“Activate” command
Select Bank C
“Activate” command
Select Bank D
“Activate” command
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
Row
A10 A12 A13 Result
(Precharge command)
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
X: Don't care
0
1
Disables Auto - Precharge (End of Burst)
Enables Auto - Precharge (End of Burst)
A12
0
A13 Result
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13
(CAS strobes)
Co1.
0
1
0
1
Enables Read/Write
commands for Bank A
0
1
1
Enables Read/Write
commands for Bank B
Enables Read/Write
commands for Bank C
Enables Read/Write
commands for Bank D
Document : 1G5-0153
Rev.1
Page16
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
