Preliminary
VG36641641BT
CMOS Synchronous Dynamic RAM
VIS
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command. When the
precharge command is asserted, the burst read operation is terminated and precharge starts.
The same bank can be activated again after t from the precharge command.
RP
When CAS latency is 2,the read data will remain valid until one clock after the precharge com-
mand.
When CAS latency is 3, the read data will remain valid until two clocks after the precharge com-
mand.
Precharge Termination in READ Cycle
Burst lengh= X
T8
T7
T0
T1
T3
T6
T2
T4
T5
CLK
Read
PRE
Q2
ACT
Command
CAS latency=2
Hi-Z
Q0
Q3
tRP
DQ
Q1
command
Read
PRE
ACT
Hi-Z
tRP
CAS latency=3
DQ
Q0
Q3
Q2
Q1
Document : 1G5-0127
Rev2
Page26
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
