Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
Read and Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
CS
RAS
CAS
WE
A11(BS)
RAa
A10
A0~A9
CAb
RAa
CAa
CAc
DQM
DQ
Hi-Z
DAb0
Write
QAa3
DAb1
DAb3
QAc0 QAc1
QAa1
QAa0
QAc3
QAa2
Read
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank A
The Write Data
The Read Data
is Masked with
Two Clocks
Latency
Command is Masked with a
Bank A
Zero Clock
latency
Document:1G5-0160
Rev.1
Page 50