Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
Interleaved Column Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
CS
RAS
CAS
WE
A11(BS)
RAa
RAa
RBa
RBa
A10
A0~A9
CBa
CBb
CBc
CAb
CBb
CAa
t
t
t
RCD
RP
DPL
DQM
DQ
t
RRD
Hi-Z
DBa0 DBa1 DBb0
DBc0 DBc1 DAb0 DBd0 DBd1 DBd2 DBd3
DAb1
DAa3
DBb1
DAa0 DAa1
DAa2
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Write
Write
Precharge
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
Activate
Command
Bank B
Command
Bank B
Command
Bank B
Write
Command
Bank B
Document:1G5-0160
Rev.1
Page 54