Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
Random Row Write (Interleaving Banks) (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK2
High
CS
RAS
CAS
WE
A11(BS)
RAa
RAb
A10
RBa
A0~A9
RBa
RAa
CBa
RAb
CAa
CAb
t
t
t
t
RCD
DPL
DPL
RP
DQM
DQ
Hi-Z
QAa5
QAa0
Write
QAa4
QAa6 QAa7 QBa0 QBa1 QBa2
Precharge
DAb2
DAb3 DAb4
DAb0 DAb1
QAa1 QAa2
QBa3 QBa4
QBa6 QBa7
QBa5
QAa3
Activate
Command
Bank A
Write
Command
Bank A
Active
Command
Bank A
Activate
Command
Bank B
Command
Bank A
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Document:1G5-0160
Rev.1
Page 48
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
