Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
10.2.2 PRECHARGE TERMINATION in WRITE Cycle
During a WRITE cycle, the BURST WRITE operation can be terminated by a PRECHARGE
command. when the PRECHARGE command is asserted, the BURST WRITE operation in imme-
diately terminated and PRECHARGE starts.
The same bank can be activated again after tRP(min.) from the PRECHARGE command. The
DQM must be high to mask invalid data in.
When CAS latency is 2 or 3, the data written prior to the PRECHARGE command will be cor-
rectly stored. However, invalid data may be written at the same clock as the PRECHARGE com-
mand. To prevent this from happening, DQM must be high at the same clock as the PRECHARGE
command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
T8
T7
T0
T1
T3
T6
T2
T4
T5
CLK
Write
PRE
ACT
Command
CAS latency=2
DQM
Hi-Z
DQ
D0
D3
D2
D4
D1
tRP
command
Write
PRE
ACT
CAS latency=3
DQM
Hi-Z
DQ
D0
D3
D2
D4
D1
tRP
Document:1G5-0160
Rev.1
Page 27