Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
8.2 WRITE with AUTO PRECHARGE
During a WRITA cycle, the AUTO PRECHARGE starts at tDPL(min.) after the last data word input to
the device
WRITE with AUTO PRECHRGE
Burst lengh=4
T7
T0
T1
T3
T6
T8
T2
T4
T5
CLK
Command
WRITA B
AUTO PRECHARGE starts
tDPL
CAS latency=2
DQ
Hi-Z_
DB0
DB1
DB2
DB3
AUTO PRECHARGE starts
WRITA B
DB0
Command
tDPL
CAS latency=3
Hi-Z
DQ
DB1
DB3
DB2
Remark WRITA means WRITE with AUTO PRECHARGE
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is
valid.
In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency
2
READ
-1
WRITE
+tDPL(min.)
3
-2
+tDPL(min)
Document:1G5-0160
Rev.1
Page 21
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
