Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
5.1 Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence(decimal)
0
1
0,1
1,0
0,1
1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence(decimal)
00
01
10
11
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
Sequential Addressing
Sequence (decimal)
Interl
eave Addressing
Sequence(decimal)
000
001
010
011
100
101
110
111
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of sequential addressing, with the length being 512/
256 words for 2Mx8/1Mx16 devices, respectively.
Document:1G5-0160
Rev.1
Page 17