Preliminary
VG3617161DT
16Mb CMOS Synchronous Dynamic RAM
VIS
5.Mode Register
1
11
0
10
0
8
0
3
2
2
2
9
0
7
1
6
6
6
4
4
0
0
0
5
5
Reserved Test Set
1
11
x
10
x
8
0
3
WT
9
1
7
0
Burst Read and Single Write
X=Dont’ care
LTMODE
BL
1
11
x
10
x
8
0
5
3
WT
9
0
7
0
4
Mode Register Set
LTMODE
BL
Bits2-0
000
WT=1
1
WT=0
1
2
4
8
001
010
011
100
101
110
111
2
4
8
Burst length
R
R
R
R
R
R
R
Full page
0
1
Sequential
Interleave
Wrap type
Bits6-4
000
CAS Iatency
R
R
2
001
010
011
100
101
110
111
3
Latency
mode
R
R
R
R
Remark R:Reserved
Document:1G5-0160
Rev.1
Page 16